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STHS4257A, STHS4257A1 STHS4257L, STHS4257L1
IEEE 802.3af PoE Powered Device (PD) interface controller with integrated signature resistor
Features

IEEE 802.3af-compliant interface for Powered Devices (PDs) Integrated 100V, 450mA power MOSFET low side switch Inrush current limit Normal operation current limit Integrated 25k signature resistor Signature disable (STHS4257A1/L1) Resistor-programmable classification current (Class 0-4) Power Good output, open drain Undervoltage Lockout (UVLO) Thermal overload protection (two-step for the STHS4257A/L) Latch (L) or auto-retry (A) after repetitive thermal overload Industrial temperature range: -40 to +85C SO8 and DFN8 (3mm x 3mm) packages RoHS compliant
8 1
SO8 (M)
DFN8 3mm x 3mm (DB)
Applications

Voice over IP (VoIP) phones
Table 1.
Device options
Signature disable
Order code
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39.2 36.0 39.2 30.5 30.5 30.5 30.5
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Web cameras
WLAN access points Internet appliances POS terminals RFID readers
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UVLO threshold, rising (V)
UVLO threshold, falling (V)
Protection mode
Thermal overload protection 2 steps 1 step 2 steps 1 step
Inrush current limit (mA, typ)
Normal operation current limit (mA, typ)
Auto Auto Latch Latch
350/188 (1) 140 350/188 140
(1)
STHS4257A1 STHS4257L STHS4257L1
375
36.0
375
1. Current limit is common for both modes and gets reduced only in case of thermal overload. See Table 5: Electrical parameters.
July 2007
Rev 4
1/18
www.st.com 1
Contents
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 Classification (RCLASS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power supply (GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signature disable input (SIGDISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Good output (PWRGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Negative power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2
IEEE802.3af PD power classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 3 4 5 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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uc d Package mechanical data . . . . . . . . . . . . . . . . . . . . . . .ro . . . . . . . . . . 14 ... e. . P. . . . . . . . . . . . . . 16 Part numbering . . . . . . . . . . . . . . . . . . . . . . . .t . . . le . o Revision history . . . . . . . . . . . . . .bs . . . . . . . . . . . . . . . . . . . . . . . . . 17 .... -O (s) ct du ro P ete ol
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 IEEE802.3af PD power classes and corresponding RCLASS values. . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SO8 - 8-lead plastic small outline, 150mils width, mechanical data. . . . . . . . . . . . . . . . . . 14 DFN8 - 8-lead dual flat no-lead outline, package mechanical data . . . . . . . . . . . . . . . . . . 15 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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List of figures
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections (STHS4257A/L, top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections (STHS4257A1/L1, top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application circuit overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram (STHS4257A/L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical application circuit (STHS4257A/L) with a DC/DC converter. . . . . . . . . . . . . . . . . . . 9 Block diagram (STHS4257A1/L1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical application circuit (STHS4257A1/L1) with a DC/DC converter. . . . . . . . . . . . . . . . 10 SO8 - 8-lead plastic small outline, 150mils width, mechanical drawing . . . . . . . . . . . . . . . 14 DFN8 - 8-lead dual flat no-lead outline, package mechanical drawing . . . . . . . . . . . . . . . 15
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STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Summary description
1
Summary description
The STHS4257 is an IEEE802.3af-compliant family of interface controllers for Power over Ethernet (PoE) Powered Device (PD) applications. The devices consist of two main sections:

The IEEE802.3af interface to the PoE powered RJ-45 wall socket, and the Hot Swap Controller (HSC) functions required to protect the PD during insertion, operation, and withdrawal from the RJ-45 socket.
These devices have an integrated high voltage power MOSFET (low-side switch) with low RON and the capability to accept transients as high as 100V. Since the pins (such as GND and VIN) which interface to the RJ-45 socket can routinely see high peak voltages in excess of 100V, it is strongly recommended that board designers protect the PD device with a transient voltage suppressor, such as the SMAJ58A (available from STMicroelectronics), connected between the GND and VIN pins (see Figure 4 on page 8). The IEEE802.3af-compliant interface includes the basic PD detection and Classification functions, whereas the `Hot Swap' functions include other basic features, such as Inrush Current Limiting, Undervoltage Lockout (UVLO), and Thermal Overload Protection. All of the devices include an open drain Power Good (PWRGD) signal to indicate normal steady operation (see Figure 1 on page 6 and Table 2 on page 6). The STHS4257 family also incorporates a 1.5V voltage offset (two series diodes) to accommodate the input diode bridge used to make the PD polarity insensitive. The STHS4257A1/L1 includes a dual level current limit circuit. This allows the STHS4257A1/L1 to interface with legacy Power over Ethernet (LAN) systems while maintaining compatibility with the current IEEE 802.3af specification. Each of the two basic part types, the STHS4257A/L and the STHS4257A1/L1, is available either with Latched Operation (L) Mode or with Automatic Retry (A) Mode after fault conditions. For product options overview see Table 1 on page 1.
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Summary description Figure 1. Logic diagram
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
GND
SIGDISA(1) RCLASS
STHS4257A/L STHS4257A1/L1
PWRGD VOUT
VIN
AI12214a
1. STHS4257A1 and STHS4257L1 devices only.
Table 2.
Signal names
Pin Symbol Description No Connect Classification pin
STHS4257A/L STHS4257A1/L1 1, 3, 7 2 4 5 6 -- 8 1, 3 2 4 5 6 7 8 NC RCLASS VIN VOUT PWRGD SIGDISA GND
Negative return power line to PSE Power Output (negative rail)
Power Good Output, open drain, active-low (referenced to VIN)
Figure 2.
Pin connections (STHS4257A/L, top view)
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Figure 3.
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NC RCLASS NC VIN
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1 2 3 4
Signature Disable Input, internally pulled to VIN
Positive Power Supply; common input/output power rail
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8 7 6 5 GND NC
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PWRGD VOUT
AI12204b
Pin connections (STHS4257A1/L1, top view)
NC RCLASS NC VIN 1 2 3 4 8 7 6 5 GND SIGDISA PWRGD VOUT
AI12205b
6/18
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Summary description
1.1
1.1.1
Pin descriptions
Classification (RCLASS)
This is the Classification pin. Connect a Classification resistor between this pin and VIN to tell the PSE which power class will be connected. Leave it open for Class 0. Note: Do not connect this pin directly to VIN. For power classes and RCLASS resistor values, see Table 3.
1.1.2
VIN
This is negative return power line to PSE.
1.1.3
Power supply (GND)
This is the Power Input/Output, positive rail.
1.1.4
Signature disable input (SIGDISA)
This pin is internally pulled down to VIN to present a valid signature to PSE. Connect to VIN if it is unused. Tie to GND to present an invalid signature. Note: This signal is available for STHS4257A1 and STHS4257L1 only.
1.1.5
Power Good output (PWRGD)
This pin indicates that the STHS4257x/x1 power MOSFET is fully on and works in normal operation mode (Power Good). Open drain, low impedance means that the power is good; in all other cases, the impedance is high (referenced to VIN).
1.1.6
Negative power output (VOUT)
1.2
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This is the Power Output, negative rail. Table 3.
Class 0 1 2 3 4 Usage Max. power levels at input of PD (W) 0.44 to 12.95 0.44 to 3.84 3.84 to 6.49 6.49 to 12.95 Reserved (1) Default Optional Optional Optional Reserved
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IEEE802.3af PD power classes and corresponding RCLASS values
Nominal classification load current (mA) <5 10.5 18.5 28 40 RCLASS Resistor (, 1%) Open 124 68.1 45.3 30.9
1. Class 4 is currently reserved and should not be used.
7/18
Summary description Figure 4.
RJ-45
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Application circuit overview
TX Pair
Data to Ethernet Physical Layer Device
2x DF01S GND SMAJ58A SIGDISA(1) PWRGD C1 0.1F, 100V 100 k To DC/DC Converter
STHS4257A/L STHS4257A1/L1
RCLASS VIN
+ C2 100F, 100V
Spare Pair Spare Pair
VOUT
RCLASS
RX Pair
Data to Ethernet Physical Layer Device
1. STHS4257A1 and STHS4257L1 devices only. To disable signature, tie this pin to GND. 2. This configuration uses either data wires or spare wires for DC power.
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8/18
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1 Figure 5. Block diagram (STHS4257A/L)
Summary description
Classification Current Source NC 1 ref + - RCLASS 2 EN 25k Signature Resistor 8
GND
7
NC
NC
3 Control Circuits Power Good
6
PWRGD
ref RS VIN 4
+ -
EN
Input Current Limit Power MOSFET
Figure 6.
Typical application circuit (STHS4257A/L) with a DC/DC converter
48V from power sourcing equipment (PSE)
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SMAJ58A
Powered Device (PD)
GND VIN 5F (min) Switching + 100V C2
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AI12206c
Diode Bridge 0.1F
~ - 100V DF01S
C1
STHS4257A/L
Power Supply
RTN
PWRGD RCLASS VIN VOUT
SHDN
+ 3V to logic -
AI12207a
9/18
Summary description Figure 7.
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1 Block diagram (STHS4257A1/L1)
Classification Current Load NC 1 ref + - 9k EN 25k Signature Resistor Signature Disable 7 SIGDISA 16k 8 GND
RCLASS
2
NC
3 Control Circuits Power Good
6 PWRGD
ref1(1) ref2(2) RS VIN 4
+ -
EN
Input Current Limit Power MOSFET
1. Ref.1 = ILIMIT HIGH 2. Ref. 2 = ILIMIT LOW
Figure 8.
Typical application circuit (STHS4257A1/L1) with a DC/DC converter
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SMAJ58A
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5 VOUT
AI12208a
Powered Device (PD)
GND 5F (min) + 100V C2 VIN
STHS4257A1/L1 100
RCLASS k SIGDISA PWRGD RCLASS VIN VOUT
Switching Power Supply
SHDN RTN + 3V to logic -
AI12209a
10/18
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Absolute maximum ratings
2
Absolute maximum ratings
Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings
Parameter Input/supply voltage (1) Voltage on VOUT pin Voltage on the respective pins Voltage on RCLASS pin Power Good output current RCLASS pin current Operating ambient temperature range Storage temperature Lead solder temperature for 10 seconds, lead-free lead finish (2) Value +0.3 to -100 VIN +100 to VIN -0.3 VIN +90 to VIN -0.3 VIN +7 to VIN -0.3 10 100 -40 to 85 Unit V V V V
Symbol VIN VOUT VSIGDISA, VPWRGD VRCLASS IPWRGD IRCLASS TA TSTG TSLD
-55 to 150
1. With respect to the GND pin.
2. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for more than 30 seconds).
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mA mA C C C
11/18
Electrical parameters
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
3
Electrical parameters
Over the full operating temperature range, unless otherwise noted. Specifications common for both STHS4257x (=STHS4257A, STHS4257L) and STHS4257x1 (=STHS4257A1, STHS4257L1) product families unless otherwise noted.
Table 5.
Symbol
Electrical parameters
Parameter Maximum Operating Voltage Signature Range Classification Range Input/supply voltage - with respect to GND pin (1), (2), (3) -1.5 -12.5 Conditions Min Typ Max -57 -9.5 -21 Unit V V V V V V
VIN
UVLO Turn-On Voltage, STHS4257x1 UVLO Turn-On Voltage, STHS4257x UVLO Turn-Off Voltage
-34.8 -36.0 -37.2 -37.7 -39.2 -40.2 -29.3 -30.5 -31.5
IIN ON IIN CLASS ICLASS RSIGNATURE
Supply Current when on Supply Current During Classification Current Accuracy During Classification Signature Resistance
VIN = -48V, pins 5, 6, 7 floating VIN = -17.5V, pins 2, 7 floating, VOUT tied to GND (4) 10mA < ICLASS < 40mA, -12.5V VIN -21V (5) 0.12
0.33 0.25
0.5
-1.5V VIN -9.5V, VOUT tied to GND, IEEE 802.3af 2-point measurement (2), (6)
RINVALID VIH VIL RINPUT VPG OUT
Invalid Signature Resistance Signature Disable High Level Input Voltage Signature Disable Low Level Input Voltage Signature Disable Input Resistance
VPG TH RISE (8)
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IPG LEAK RON
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Power Good Output Low Voltage Power Good Trip Point, power good signal going inactive Power Good Leakage Current On-Resistance VOUT Pin Leakage Current Input Current Limit, High Level, STHS4257x1 (normal operation mode)
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-1.5V VIN -9.5V, SIGDISA and VOUT tied to GND, IEEE 802.3af 2-point measurement (2), (6), (7)
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mA
mA
3.5
23.25
26.00
11.8
k
With respect to VIN, high level invalidates signature (7) With respect to VIN, low level enables signature (7) With respect to VIN IPG = 1mA, VIN = -48V, PWRGD referenced to VIN
3
57 0.45
V V k
100 0.5 2.7 3.0 3.3 1 0.72 1.0 1 340 330 375 375 400 400
V V A A mA mA
VIN = -48V, voltage between VIN and VOUT, VOUT rising VPWRGD - VIN = 57V, PWRGD MOSFET off, VPWRGD = VGND (9) I = 350mA, VIN = -48V, measured from VIN to VOUT VIN = 0V, power MOSFET off, VOUT = 57V (10) VIN = -48V, VOUT = -43V (11), (12) 0C TA 70C -40C TA 85C
IOUT LEAK
ILIMIT HIGH
12/18
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1 Table 5.
Symbol ILIMIT LOW ILIMIT ILIMIT WARM TOVERTEMP TSHUTDOWN
Electrical parameters
Electrical parameters (continued)
Parameter Input Current Limit, Low Level, STHS4257x1 (inrush mode) Conditions VIN = -48V, VOUT = -43V (11), (12) Min 100 300 Typ 140 350 188 120 , , 140 Max 180 400 Unit mA mA mA C C
Input Current Limit, STHS4257x VIN = -48V, VOUT = -43V (14) Overtemperature Input Current Limit, STHS4257x Overtemperature Trip Temperature, STHS4257x Thermal Shutdown Trip Temperature
(14)
(14)
(11) (13) (14)
1. The STHS4257 family of PoE products operates with a negative supply voltage (with respect to the GND pin, unless otherwise noted). Voltages in this data sheet are always referred to in terms of absolute magnitude, thus "maximum negative voltage" means the most negative voltage and analogically "rising negative voltage" refers to a voltage that is becoming more negative. 2. The STHS4257 family of products is designed to work with two series diode drops caused by diode bridge that makes the PD input polarity-insensitive. Parameter ranges specified in the Electrical Parameters Table are with respect to STHS4257x/x1 pins and are designed to meet the IEEE 802.3af specifications when these diode drops are included. See Figure 4 on page 8.
3. The STHS4257x/x1 devices include hysteresis in the UVLO voltages to avoid any start-up oscillation. As required by IEEE 802.3af, the STHS4257 family devices will power up from a voltage source with 20 series resistance on the first trial. 4. The Supply Current During Classification (IIN CLASS) does not include classification current programmed at pin 2. Total supply current in classification mode will be IIN CLASS + ICLASS (see also Note 5). 5. ICLASS is the measured current flowing through RCLASS. ICLASS accuracy is with respect to the ideal current defined as ICLASS = 1.237/RCLASS. The current accuracy specification does not include variations in RCLASS resistance. The total classification current seen by PSE also includes the quiescent current (IIN CLASS). See Figure 4 on page 8.
6. Signature resistance is measured via the 2-point V/I method as defined by IEEE 802.3af standard. The STHS4257 device family signature resistance is offset from standard 25k to account for the series diode bridge resistance. With two series diodes, the total PD resistance will be between 23.75k and 26.25k which meets IEEE 802.3af specifications. The minimum probe voltages measured at the STHS4257x/x1 pins are -1.5 and -2.5V. The maximum probe voltages are -8.5 and -9.5V. 7. To disable the 25k signature, tie SIGDISA to GND (0.1V) or hold SIGDISA high with respect to VIN. See Figure 4 on page 8. 8. VPG TH FALL is not used: To eliminate the current peak during the transition from inrush to normal operation mode, the power MOSFET (between VOUT and VIN - see Figure 5 on page 9) turns fully on only after the inrush current decreases by 10% from its initial value (i.e. when the output capacitor is fully charged). 9. GND pin at the same potential as PWRGD pin to prevent ESD protection from impacting the measured results. To keep PWRGD MOSFET off under this condition, maintain uninterrupted inrush current e.g. by applying 1V voltage between VOUT and VIN pin. This will keep the device in inrush mode, thus preventing PWRGD from going active (on). 10. To significantly reduce IOUT LEAK and eliminate its impact on total current during detection and classification, the resistor divider used to provide feedback on VOUT - VIN voltage is disconnected below the UVLO threshold. 11. The STHS4257x1 includes thermal protection. In the event of an overtemperature condition (TSHUTDOWN is reached), the STHS4257x1 will turn off the power MOSFET until the part cools below the overtemperature limit (TOVERTEMP). The STHS4257x1 is also protected against thermal damage from incorrect classification probing by the PSE: If the STHS4257x1 temperature exceeds the shutdown trip point (TSHUTDOWN), the classification load current is disabled.
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12. The STHS4257x1 includes dual level input current limit. At turn-on, before output capacitor C2 is charged, the STHS4257x1 current level is set to the low level. After the output capacitor C2 is charged, the STHS4257x1 switches to high level current limit and remains there until the input voltage drops below the UVLO turn-off threshold.
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13. The STHS4257 family devices include overtemperature protection that is intended to protect the device during momentary overload conditions only. Continuous operation close to overtemperature limits may impair device reliability. 14. The STHS4257x includes smart thermal protection. In the event of an overtemperature condition, the STHS4257x will reduce the input current limit by 50% to reduce the power dissipation in the package. If the part continues heating and reaches the shutdown temperature (TSHUTDOWN), the current is reduced to zero until the part cools below the overtemperature limit (TOVERTEMP). The STHS4257x is also protected against thermal damage from incorrect classification probing by the PSE: If the STHS4257x temperature exceeds the shutdown trip point (TSHUTDOWN), the classification load current is disabled.
13/18
Package mechanical data
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 9. SO8 - 8-lead plastic small outline, 150mils width, mechanical drawing
h x 45 A2 B e D A C ddd
8
E
1
H
1. Drawing is not to scale.
Table 6.
Symb A
SO8 - 8-lead plastic small outline, 150mils width, mechanical data
mm
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Typ - - - - - - - 1.27 - - - -
Min
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Max 1.75 0.25 0.51 0.25 5.00 0.10 4.00 - 6.20 0.50 0.90 8
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Typ - - - - - - - 0.050 - - - -
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inches Min 0.053 0.004 0.013 0.007 0.189 - 0.150 - 0.228 0.010 0.016 0 8 Max 0.069 0.010 0.020 0.010 0.197 0.004 0.157 - 0.244 0.020 0.035 8
1.35 0.10 0.33 0.19 4.80 - 3.80 - 5.80 0.25 0.40 0 8
14/18
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Package mechanical data
Figure 10. DFN8 - 8-lead dual flat no-lead outline, package mechanical drawing
Seating Plane C A2 A E ddd C D e 1 2 3 4 A1
E2
A3
8
7
6 b
5
D2
Bottom View
1. Drawing is not to scale.
Table 7.
Symb A
DFN8 - 8-lead dual flat no-lead outline, package mechanical data
mm
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A2 A3 b D D2 ddd E E2 e L N
A1
(s) ct du
Typ 0.90 0.02 - 0.70 0.20 0.23 3.00 2.38 - 3.00 1.64 0.50 0.40 - - -
Min
-O
let so b
Max 1.00 0.05 - - 0.30 - 2.48 0.08 - 1.74 - 0.50
eP
uc rod
DFN-A
s) t(
L
inches Min 0.031 Max 0.039 0.002
Typ 0.035 0.001 0.028 0.008 0.009 0.118 0.094
0.80
0.18
0.007
0.012
2.23 - - 1.49 - 0.30 8
0.003 0.118 0.065 0.020 0.016 0.059 - 0.012 8 0.069 - 0.020
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Part numbering
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
5
Part numbering
Table 8.
Example:
Ordering information scheme
STHS 4257A1 M 6 F
Device type STHS
Product options 4257A 4257A1 4257L 4257L1
Package M = SO8 (150mils width) DB(1) = DFN8 (3mm x 3mm)
Temperature range 6 = -40 to 85C
Shipping method
F = ECOPACK Package, Tape & Reel E = ECOPACK Package, Tube
1. Contact local sales office for availability.
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For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
ro P e
t(s uc d
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ol bs
eP et
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STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Revision history
6
Revision history
Table 9.
Date 12-Jul-2006 19-Dec-2006 24-May-2007 26-Jul-2007
Document revision history
Revision 1 2 3 4 Initial release. Updated Features and Table 4. Formatting changes and updatedTable 5. Document status upgraded to full datasheet, updated cover page and Table 8. Changes
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STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
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